2018-07-06

Digital Verification Engineer
Job Opportunity at Analog Solutions

Posted on Jul 6

http://www.analogsolutions.com    +1 (865) 458-4421

Location: Irvine, CA
Job Type: Full Time
Job ID: W4163218

Job Description:

 

We are looking for a highly motivated and talented verification engineer to join a talented team to work on the next generation networking chips. Our client's product line is a fast growing business in high speed 50Gbs/100Gbs/200Gbs/400Gbs Ethernet and Optical Transport physical layer devices with very complex design challenges.

 

Job responsibilities include:

  • Architect and develop verification environment and testbench components such as BFMs and checkers.
  • Develop comprehensive test plan and implement test cases.
  • Verify design in block and chip level environment using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification.
  • Perform RTL code coverage, assertion coverage, and gate level simulations.
  • Drive and adopt new verification methodologies and flows for efficiency improvements.
  • Mentor junior engineers on project execution.

 

Job Requirements       

  • MSEE/CS/CE plus 7 years, or BSEE/CS/CE plus 9 years, equivalent experience in ASIC design and verification.
  • Experience in verifying designs at system level and block level.
  • Experience using SystemVerilog, VMM or UVM.
  • Familiar with System Verilog Assertions.
  • Strong experience in ASIC design verification flows and DV methodologies.
  • Networking domain knowledge (e.g. Ethernet, GFP, OTN).
  • Hands on design verification experience of gigabit Ethernet is a plus.
  • Strong and independent design debugging capability.
  • Strong programming and scripting language capability.
  • Highly motivated and be able to work both independently and as a member of team.
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