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SOC RTL Design Engineer
Job Opportunity at
Posted on Oct 25
+1 (865) 458-4421
The Company's platform delivers the power of desktop GPU in a single low-power chip, supporting inference for large deep neural networks. The company's technology is based upon an entirely new hybrid digital/analog flash calculation using 8-bit non-volatile memory arrays which has been under development since 2012. This step change in performance brings in a range of new applications in a broad array of verticals, including safety and security, autonomous vehicles, VR/AR, robotics and media.
The company is a fast-growing company with 60 employees, $56M in funding from top tier investors, and >$1M NRE revenue from two existing customer accounts. The company's investors include Softbank, DFJ, Lux Capital, and Data Collective.
About the role:
The company is a fast-paced startup looking for individuals that enjoy wide-reaching and flexible roles. The primary responsibility for this position is digital RTL design of the company's chips, but we are looking for individuals with strong computer architecture knowledge as well.
You will be the owner of all aspects of design and development for system-level blocks which form the SoC infrastructure. You will need to contribute, and ideally, have great ownership of, the architecture, microarchitecture, and RTL for a large high-performance system. Additionally, beyond defining what functionality these blocks provide, you will help drive methodologies to establish and enable first-pass success of these chips.
Beyond digital RTL design for our novel chip architecture, this role also presents a unique opportunity to get involved with and learn more about state-of-the-art deep neural networks (DNNs). You will also be collaborating with the system architecture, software, DFT, and analog design teams at the company.
Here's the background we hope you have:
BS/MS/PhD in EE/CS/CSE
3-5+ years of industry experience
RTL, microarchitecture, and architecture experience on advanced SoCs
Experience with Design for Test (DFT) and Design for Debug (DFD) logic such as fuse controllers, memory BIST, scan dump, etc.
Experience with clocking and reset methodologies
Understanding of timing constraints
The following would be nice to have, but is not required:
Experience working at startups
Experience with RTL design for clock domain crossings
Experience with Python or Ruby
Experience working with a regression system
Experience working with a revision control system
Comfortable working from command line
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