Static Timing Analysis Engineer
Job Opportunity at Analog Solutions

Posted on Jul 27

http://www.analogsolutions.com    +1 (865) 458-4421

Location: San Jose, CA
Job Type: Full Time
Job ID: W4164732

The selected candidate will design, implement, and deploy solutions mainly based on TCL, Perl, and Unix shell. Would will also be running extensive and complex studies on digital circuits using industry standard SSTA tools and standard cell libraries with variation information. Industry experience in statistical data analysis, and script development in Unix is required. Experience in transistor level simulation and characterization, ASIC design process such as physical implementation, timing closure, tape-out, and post-silicon analysis is a bonus.


Candidate will also work on long term projects with external EDA tool vendors as well as internal partners and customers on a regular basis. Excellent communication, relationship management, and leadership skills are essential. Candidate must have the ability to prioritize well, communicate clearly, deliver solutions on-time, work well with external and internal partners, and possess advanced IC design engineering skills. The candidate will be expected to work across multiple facets of projects and juggle multiple responsibilities at the same time.


Qualifications: The must haves are the following:

The four must-haves for this role are:
  • SSTA: Statistical Static Timing Analysis using Synopsys Primetime and Cadence Tempus tools 
  • TCL
  • Perl
  • Statistical data analysis

The minimum engineering experience required is typically a BS degree in EE/CS with 12+ years of industry experience, or an MS degree or Ph.D. degree in EE/CS with 10+/7+ years of industry experience.

  • Strong and hands-on experience with industry standard SSTA tools such as Primetime and Tempus.
  • Strong and hands-on experience developing scripts in TCL, Perl, Unix shell and flow automation.
  • Strong and hands-on experience with statistical data analysis.
  • Industry experience with standard cell library characterization and CMOS digital circuit simulation
  • Strong analytical skills and extremely detail oriented.
  • Strong communication skills.
  • Strong multitasking skills.
  • Optimistic yet pragmatic attitude.
  • Demonstrable skills for quick ramp-up.
  • Extremely detailed oriented, organized and methodical.
  • Ability to stay calm under extreme pressure.
  • Team player.
  • Able to work with minimum supervision and handle ambiguity.
Selling points:
They are a central team focused on timing sign-off with the focus on modeling the physical phenomena (at ultra-deep sub-micron technology nodes) that cannot be captured in the usual .lib standard cell libraries. We put methodologies together that we call it the 'recipe' that guarantees successful tape-out without being too pessimistic. For this role, knowing the STA tools (Primetime and Tempus) really well is key and how to use the tool commands and work with the database in the tool to apply certain margins would be desired. I'd say the potential candidates would be the people who drive the STA methodologies in the back-end teams or even application engineers or people behind the tools (at Synopsys or Cadence) who know their STA tools very well.
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