| Sr. RFIC Design Eng. |
Job Id: W188466 |
Posted On: 11/25/2009 |
|
Location: Austin, TX;
Job Type: Full Time
Salary: $130000.00 to $150000.00/year
Degree: Master of Science
|
|
DescriptionSr. RFIC Design Engineer
This well funded Pre-IPO company, Headquartered in Austin, TX, was founded and is staffed by some of the top Executive, Engineering, Marketing and Sales Professionals in the Industry. Their experience in Wireless technologies includes: Transceivers, CMOS P/As, UWB and unique Multi-Chip Packaging Technologies. The companys fabless manufacturing model provides tremendous flexibility with wafer process technology choices and allows us to partner with the worlds largest and most respected semiconductor manufacturing companies. Reporting to the VP of Engineering, the chosen candidate will lead and contribute to the Architecture & Design of CMOS RF Systems and Circuits. This will include: Transistor Level Design, Passive and Distributed Circuit Design, Custom Layout, Test, Evaluation and De-Bugging of RFICs. For this reason, and extensive and broad RFIC Design Background is required. Experience with Architecture and Design Trade-offs a must.
Description: Detailed design of CMOS RF systems and circuits, from architecture to transistor-level including passive/distributed circuit design. Experience with custom layout of high performance RF circuits is required. Must be able to plan and execute design, layout and evaluation tasks. Good communication skills and a demonstrated track record of success are essential. Experience with test, evaluation and debugging of prototype ICs and design support for mass production is required.
Education: MSEE or PhD
Experience: 7+ years in wireless semiconductor CMOS RF or CMOS RFIC design.
Skills:
Architects, designs, and verifies circuits, systems, and algorithms to meet product requirements
Works as senior member of the design term, and leads and mentors junior design engineers, makes design trade-offs in chip architecture and block level circuit topology, and determines design approaches and parameters
Develops innovative new designs for patenting or protecting as trade secret
Responsible for custom layout as needed, including interaction with layout designers
Strong knowledge of IC design flow and product cycle
Demonstrated success from product concept through full production
Advanced on-chip, package and printed circuit board (PCB) parasitic analysis knowledge
Advanced MOS device modeling skills
Good knowledge of CMOS fabrication processes
Advanced knowledge of MOS transistors and analog/digital circuit design
Experience with on-chip, package and printed circuit board (PCB) parasitic and design issues
Proficient with such tools as Cadance and SpectreRF, layout tools such as Virtuoso and Assura and/or Calibre.
Proficient in RF testing and debugging
Experience with 3D electromagnetic solvers and microwave design tools such as ADS is a plus
|
New Users - Register Here to Apply |
|
Returning Users - Login to Apply |
 | Post your resume |
| Create Career Alert emails to receive fresh jobs daily |
| Sign Up Now |
|
|
|
|
|
|